- 5 Results
Lowest price: € 107.09, highest price: € 130.89, average price: € 113.19
1
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Order
at Springer.com
€ 107.09
Order
Details & Shipping
Sponsored link
Nikhil Jayakumar; Suganth Paul; Rajesh Garg:

Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909503

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for p… More...

  - new in stock. Shipping costs:zzgl. Versandkosten., plus shipping costs
close (x)
2
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Order
at Springer.com
€ 107.09
Order
Details & Shipping
Sponsored link

Nikhil Jayakumar; Suganth Paul; Rajesh Garg:

Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909503

Engineering; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design ASIC, EDA, Electronic Design Automation, Leakage, Low Power Design, Sub-threshold logic, Transistor, VL… More...

  - This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Shipping costs:zzgl. Versandkosten., plus shipping costs
close (x)
3
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Order
at Springer.com
€ 107.09
Order
Details & Shipping
Sponsored link
Nikhil Jayakumar; Suganth Paul; Rajesh Garg:
Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909503

Engineering; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design ASIC, EDA, Electronic Design Automation, Leakage, Low Power Design, Sub-threshold logic, Transistor, VL… More...

  - This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Shipping costs:zzgl. Versandkosten., plus shipping costs
close (x)
4
Minimizing and Exploiting Leakage in VLSI Design - Hugo Pinto
Order
at hive.co.uk
£ 101.58
(aprox. € 113.78)
Order
Details & Shipping
Sponsored link
Hugo Pinto:
Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909503

This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the s… More...

  - No. 9781441909503. Shipping costs:Instock, Despatched same working day before 3pm, zzgl. Versandkosten., plus shipping costs
close (x)
5
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Order
at lehmanns.de
€ 130.89
Shipment: € 0.001
Order
Provider details
Sponsored link
Nikhil Jayakumar; Suganth Paul; Rajesh Garg:
Minimizing and Exploiting Leakage in VLSI Design - First edition

2009, ISBN: 9781441909503

[ED: 1], Auflage, eBook Download (PDF), eBooks, [PU: Springer-Verlag]

Shipping costs:Download sofort lieferbar, , Versandkostenfrei innerhalb der BRD. (EUR 0.00)
close (x)
1As some platforms do not transmit shipping conditions to us and these may depend on the country of delivery, the purchase price, the weight and size of the item, a possible membership of the platform, a direct delivery by the platform or via a third-party provider (Marketplace), etc., it is possible that the shipping costs indicated by find-more-books.com / find-more-books.com do not correspond to those of the offering platform.

Bibliographic data of the best matching book

Details of the music title
Minimizing and Exploiting Leakage in VLSI Design
Author:
Title:
ISBN:

9781441909503

Details of the CD - Minimizing and Exploiting Leakage in VLSI Design


EAN (ISBN-13): 9781441909503
ISBN (ISBN-10): 1441909508
Publishing year: 2009
Publisher: Springer-Verlag
214 Pages
Language: eng/Englisch

CD in our database since 2012-03-25T17:47:37-04:00 (New York)
Detail page last modified on 2020-03-10T15:48:44-04:00 (New York)
EAN: 9781441909503

EAN - alternate spelling:
1-4419-0950-8, 978-1-4419-0950-3
Alternate spelling and related search-keywords:
CD artist: sunil, garg
CD title: vlsi, mini design

Information from Publisher

Author: Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Title: Minimizing and Exploiting Leakage in VLSI Design
Publisher: Springer; Springer US
214 Pages
Publishing year: 2009-12-02
New York; NY; US
Language: English
106,99 € (DE)
110,00 € (AT)
130,00 CHF (CH)
Available
XXVII, 214 p.

EA; E107; eBook; Nonbooks, PBS / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; ASIC; EDA; Electronic Design Automation; Leakage; Low Power Design; Sub-threshold logic; Transistor; VLSI; VLSI Design; integrated circuit; C; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Engineering; Computer-Aided Design (CAD); BC

Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).
Provides a variety of approaches to control and exploit leakage Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues Presents a new, practical self-compensated, closed loop approach to controlling leakage, via sub-threshold circuits, which yields upwards of 20X power savings

More/other books that might be very similar to this book

Latest similar book:
9781441909497 Minimizing and Exploiting Leakage in VLSI Design (Jayakumar, Nikhil; Paul, Suganth; Garg, Rajesh)

< to archive...