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Designing Reliable and Efficient Networks on Chips / Srinivasan Murali / Buch / Lecture Notes in Electrical Engineering / Gb / Englisch / 2009 / Springer Netherland / EAN 9781402097560 - Murali, Srinivasan
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Murali, Srinivasan:

Designing Reliable and Efficient Networks on Chips / Srinivasan Murali / Buch / Lecture Notes in Electrical Engineering / Gb / Englisch / 2009 / Springer Netherland / EAN 9781402097560 - hardcover

2009, ISBN: 9781402097560

[ED: Gebunden], [PU: Springer Netherland], Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum p… More...

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Designing Reliable and Efficient Networks on Chips Srinivasan Murali Buch Lecture Notes in Electrical Engineering Gb Englisch 2009 Springer Netherland EAN 9781402097560 - Murali, Srinivasan
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Murali, Srinivasan:

Designing Reliable and Efficient Networks on Chips Srinivasan Murali Buch Lecture Notes in Electrical Engineering Gb Englisch 2009 Springer Netherland EAN 9781402097560 - hardcover

2009, ISBN: 9781402097560

[ED: Gebunden], [PU: Springer Netherland], Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum p… More...

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Designing Reliable and Efficient Networks on Chips / Srinivasan Murali / Buch / X / Englisch / 2009 / SPRINGER NATURE / EAN 9781402097560 - Murali, Srinivasan
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Murali, Srinivasan:
Designing Reliable and Efficient Networks on Chips / Srinivasan Murali / Buch / X / Englisch / 2009 / SPRINGER NATURE / EAN 9781402097560 - hardcover

2009

ISBN: 9781402097560

[ED: Gebunden], [PU: SPRINGER NATURE], Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power… More...

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Designing Reliable and Efficient Networks on Chips 2009 - Murali, Srinivasan
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Designing Reliable and Efficient Networks on Chips 2009 - used book

2009, ISBN: 9781402097560

2009 Neubindung, Ausgabe 2009 4947336/12 Versandkostenfreie Lieferung metal-oxide-semiconductor transistor,Topology,Reliability,Design,Systems on Chips,Networks on Chips,integrated circui… More...

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Designing Reliable and Efficient Networks on Chips - Murali, Srinivasan
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2009, ISBN: 9781402097560

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Designing Reliable and Efficient Networks on Chips
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ISBN:

9781402097560


Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

Details of the book - Designing Reliable and Efficient Networks on Chips


EAN (ISBN-13): 9781402097560
ISBN (ISBN-10): 1402097565
Hardcover
Publishing year: 2009
Publisher: Springer-Verlag New York Inc.
198 Pages
Weight: 0,459 kg
Language: eng/Englisch

Book in our database since 2009-11-23T17:18:50-05:00 (New York)
Detail page last modified on 2024-01-30T13:53:06-05:00 (New York)
ISBN/EAN: 9781402097560

ISBN - alternate spelling:
1-4020-9756-5, 978-1-4020-9756-0
Alternate spelling and related search-keywords:
Book author: srinivasan
Book title: designing, chips, electrical engineering

Information from Publisher

Author: Srinivasan Murali
Title: Lecture Notes in Electrical Engineering; Designing Reliable and Efficient Networks on Chips
Publisher: Springer; Springer Netherland
198 Pages
Publishing year: 2009-04-21
Dordrecht; NL
Printed / Made in
Language: English
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD
X, 198 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Design; Networks on Chips; Reliability; Systems on Chips; Topology; integrated circuit; metal-oxide-semiconductor transistor; Electronic Circuits and Systems; Electrical Power Engineering; Processor Architectures; Elektrotechnik; Rechnerarchitektur und Logik-Entwurf; BC

NoC Design Methods.- Designing Crossbar Based Systems.- Netchip Tool Flow for NoC Design.- Designing Standard Topologies.- Designing Custom Topologies.- Supporting Multiple Applications.- Supporting Dynamic Application Patterns.- NoC Reliability Mechanisms.- Timing-Error Tolerant NoC Design.- Analysis of NoC Error Recovery Schemes.- Fault-Tolerant Route Generation.- NoC Support for Reliable On-Chip Memories.- Conclusions and Future Directions.
First book that presents in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs Presents an integrated flow to design interconnect architectures that can lead to faster time-to-market and design closure Shows evolution of design methods from complex crossbar based buses to NoCs Presents static and run-time methods for achieving reliable operation of the NoC and the entire system Includes supplementary material: sn.pub/extras

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