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Formal Semantics for VHDL (The Springer Interna, Kloos, Kloos, Breuer-, - Carlos Delgado Kloos
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Carlos Delgado Kloos:

Formal Semantics for VHDL (The Springer Interna, Kloos, Kloos, Breuer-, - hardcover

ISBN: 9780792395522

Author: Carlos D. Kloos, Carlos Delgado Kloos, P. Breuer ISBN 10: 0792395522. Title: Formal Semantics for VHDL (The Springer International Series in Engineering and Item Condition: New. P… More...

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Formal Semantics for VHDL - 9780792395522 - P. Breuer, Carlos Delgado Kloos
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P. Breuer, Carlos Delgado Kloos:

Formal Semantics for VHDL - 9780792395522 - hardcover

ISBN: 9780792395522

ISBN-13: 9780792395522, 978-0792395522. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semant… More...

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Formal Semantics for VHDL
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Formal Semantics for VHDL - new book

ISBN: 9780792395522

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the la… More...

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Formal Semantics for VHDL - Paperback

ISBN: 9780792395522

*Formal Semantics for VHDL* - Auflage 1995 / gebundene Ausgabe für 131.99 € / Aus dem Bereich: Bücher, Ratgeber, Computer & Internet Medien > Bücher nein Buch (gebunden) Hardcover;Naturwi… More...

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Delgado Kloos, Peter T. Breuer, Delgado Kloos et P.T. Breuer:
Formal Semantics for Vhdl - hardcover

1995, ISBN: 9780792395522

Springer, 1995. Hardcover. Good. Former library book. Slight signs of wear on the cover. Edition 1995. Ammareal gives back up to 15% of this item's net price to charity organizations., … More...

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Details of the book
Formal Semantics for VHDL

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.

Details of the book - Formal Semantics for VHDL


EAN (ISBN-13): 9780792395522
ISBN (ISBN-10): 0792395522
Hardcover
Paperback
Publishing year: 1995
Publisher: SPRINGER NATURE
264 Pages
Weight: 0,553 kg
Language: eng/Englisch

Book in our database since 2007-06-16T21:20:31-04:00 (New York)
Detail page last modified on 2023-11-01T17:22:36-04:00 (New York)
ISBN/EAN: 9780792395522

ISBN - alternate spelling:
0-7923-9552-2, 978-0-7923-9552-2
Alternate spelling and related search-keywords:
Book author: kloos, springer, breuer, carlos delgado
Book title: formal semantics, semantics science, peter breuer, vhdl


Information from Publisher

Author: Carlos Delgado Kloos; P. Breuer
Title: The Springer International Series in Engineering and Computer Science; Formal Semantics for VHDL
Publisher: Springer; Springer US
249 Pages
Publishing year: 1995-02-28
New York; NY; US
Weight: 1,220 kg
Language: English
106,99 € (DE)
109,99 € (AT)
118,00 CHF (CH)
POD
XIV, 249 p.

BB; Circuits and Systems; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; C programming language; Hardware; Hardwarebeschreibungssprache; Standard; System; VHDL; formal method; logic; verification; Programming Languages, Compilers, Interpreters; Theory of Computation; Computer Hardware; Artificial Intelligence; Electrical Engineering; Electronic Circuits and Systems; Compilers and Interpreters; Theory of Computation; Computer Hardware; Artificial Intelligence; Electrical and Electronic Engineering; Compiler und Übersetzer; Theoretische Informatik; Computerhardware; Künstliche Intelligenz; Elektrotechnik; BC; EA

Foreword. Preface. 0. Giving Semantics to VHDL: an Introduction; C. Delgado Kloos, P.T. Breuer. 1. A Functional Semantics for Delta-Delay VHDL Based on Focus; M. Fuchs, M. Mendler. 2. A Functional Semantics for Unit-Delay VHDL; P.T. Breuer, L. Sánchez Fernanández, C. Delgado Kloos. 3. An Operational Semantics for a Subset of VHDL; J.P. Van Tassel. 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines; E. Börger, U. Glässer, W. Müller. 5. A Formal Model of VHDL Using Coloured Petri Nets; S. Olcoz. 6. A Deterministic Finite-State Model for VHDL; G. Döhmen, R. Herrmann. 7. A Flow Graph Semantics of VHDL: a Basis for Hardware Verification with VHDL; R. Reetz, T. Kropf. References.

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