English
United States
Sign in
Tip from find-more-books.com
Similar books
More/other books that might be very similar to this book
Search tools
Book recommendations
Latest news
Advertising
FILTER
- 0 Results
Lowest price: 110.73 €, highest price: 180.31 €, average price: 146.24 €
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri
book is out-of-stock
(*)
Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri:
Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909497

ID: 618814a823586f881a52a66c86ff8826

This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. Bücher / Fremdsprachige Bücher / Englische Bücher 978-1-4419-0949-7, Springer

New book Buch.de
Nr. 17593450 Shipping costs:Bücher und alle Bestellungen die ein Buch enthalten sind versandkostenfrei, sonstige Bestellungen innerhalb Deutschland EUR 3,-, ab EUR 20,- kostenlos, Bürobedarf EUR 4,50, kostenlos ab EUR 45,-, Sofort lieferbar, más costos de envío, plus shipping costs
Details...
(*) Book out-of-stock means that the book is currently not available at any of the associated platforms we search.
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri
book is out-of-stock
(*)
Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri:
Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909497

ID: 7200646

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, Springer

New book Thalia.de
No. 17593450 Shipping costs:, Sofort lieferbar, DE (EUR 0.00)
Details...
(*) Book out-of-stock means that the book is currently not available at any of the associated platforms we search.
Minimizing and Exploiting Leakage in VLSI Design - Jayakumar, Nikhil / Paul, Suganth / Garg, Rajesh
book is out-of-stock
(*)
Jayakumar, Nikhil / Paul, Suganth / Garg, Rajesh:
Minimizing and Exploiting Leakage in VLSI Design - used book

ISBN: 9781441909497

ID: 6748512

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. Minimizing and Exploiting Leakage in VLSI Design Jayakumar, Nikhil / Paul, Suganth / Garg, Rajesh, Springer

Used or antiquarian book Betterworldbooks.com
Shipping costs: EUR 0.00
Details...
(*) Book out-of-stock means that the book is currently not available at any of the associated platforms we search.
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar
book is out-of-stock
(*)
Nikhil Jayakumar:
Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909497

[ED: Buch], [PU: Springer-Verlag GmbH], Neuware - Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. -, [SC: 0.00], Neuware, gewerbliches Angebot, 243x155x23 mm, [GW: 510g]

New book Booklooker.de
Sparbuchladen
Shipping costs:Versandkostenfrei, Versand nach Deutschland (EUR 0.00)
Details...
(*) Book out-of-stock means that the book is currently not available at any of the associated platforms we search.
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar
book is out-of-stock
(*)
Nikhil Jayakumar:
Minimizing and Exploiting Leakage in VLSI Design - new book

ISBN: 9781441909497

[ED: Buch], [PU: Springer-Verlag GmbH], Neuware - Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic., [SC: 0.00], Neuware, gewerbliches Angebot, 243x155x23 mm, [GW: 510g]

New book Booklooker.de
Carl Hübscher GmbH
Shipping costs:Versandkostenfrei, Versand nach Deutschland (EUR 0.00)
Details...
(*) Book out-of-stock means that the book is currently not available at any of the associated platforms we search.

Details of the book
Minimizing and Exploiting Leakage in VLSI Design

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

Details of the book - Minimizing and Exploiting Leakage in VLSI Design


EAN (ISBN-13): 9781441909497
ISBN (ISBN-10): 1441909494
Hardcover
Publishing year: 2010
Publisher: Springer-Verlag GmbH
214 Pages
Weight: 0,510 kg
Language: eng/Englisch

Book in our database since 17.12.2007 05:54:55
Book found last time on 15.05.2017 10:56:10
ISBN/EAN: 1441909494

ISBN - alternate spelling:
1-4419-0949-4, 978-1-4419-0949-7


< to archive...
Related books