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Digital Timing Macromodeling for VLSI Design Verification - Jeong-Taek Kong#David V. Overhauser
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Jeong-Taek Kong#David V. Overhauser:

Digital Timing Macromodeling for VLSI Design Verification - new book

ISBN: 9780792395805

ID: 0c5a772a8e0f46f2026f5bc6903ad06d

Digital Timing Macromodeling for VLSI Design Verification Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Bücher / Fremdsprachige Bücher / Englische Bücher 978-0-7923-9580-5, Springer

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Digital Timing Macromodeling for VLSI Design Verification - Jeong-Taek Kong#David V. Overhauser
book is out-of-stock
(*)

Jeong-Taek Kong#David V. Overhauser:

Digital Timing Macromodeling for VLSI Design Verification - new book

ISBN: 9780792395805

ID: 107763359

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Digital Timing Macromodeling for VLSI Design Verification Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, Springer

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Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Kong, Jeong-Taek; Overhauser, David
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Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - First edition

1995

ISBN: 0792395808

Hardcover, ID: 7059172888

[EAN: 9780792395805], Usato, ottimo stato, [SC: 17.4], [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], Technology|Electronics|Circuits|General, Technology|Electronics|Circuits|VLSI, Computers & the Internet|CAD-CAM, White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T

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Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Kong, Jeong-Taek; Overhauser, David
book is out-of-stock
(*)
Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - First edition

1995, ISBN: 0792395808

Hardcover, ID: 7059172888

[EAN: 9780792395805], Gebraucht, sehr guter Zustand, [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], Technology|Electronics|Circuits|General, Technology|Electronics|Circuits|VLSI, Computers & the Internet|CAD-CAM, White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T

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PsychoBabel & Skoob Books, Abingdon, OXON, United Kingdom [2917279] [Rating: 5 (von 5)]
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Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Kong, Jeong-Taek; Overhauser, David
book is out-of-stock
(*)
Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - hardcover

1995, ISBN: 9780792395805

ID: 488848473

Norwell, Massachusetts, U.S.A.: Kluwer Academic Publishers, 1995. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. First Edition. hardcover. Very Good/No Dust Jacket. Used., Kluwer Academic Publishers, 1995

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Details of the book
Digital Timing Macromodeling for VLSI Design Verification
Author:

Overhauser, David V.; Kong, Jeong-Taek

Title:

Digital Timing Macromodeling for VLSI Design Verification

ISBN:

0792395808

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

Details of the book - Digital Timing Macromodeling for VLSI Design Verification


EAN (ISBN-13): 9780792395805
ISBN (ISBN-10): 0792395808
Hardcover
Publishing year: 1995
Publisher: Springer-Verlag GmbH
292 Pages
Weight: 0,602 kg
Language: eng/Englisch

Book in our database since 21.10.2007 19:40:29
Book found last time on 29.09.2016 03:10:17
ISBN/EAN: 0792395808

ISBN - alternate spelling:
0-7923-9580-8, 978-0-7923-9580-5

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